When developing new generations of semiconductor devices, for example vertical power transistors or DMOS power transistors (DMOS=double diffused metal oxide semiconductor), the provision of top quality and reliability of the components is an important goal. Therefore, the latest generations of transistors have to undergo the most stringent reliability tests before they are delivered. In this context, one important test is temperature cycling (TC). During this test, the interaction between the chip, or die, which is mostly made of semiconductor material, insulators and metals, and the housing, mostly made of plastics, is tested. In particular, in the case of this test, the behavior of the finished device after molding or after the packaging process is examined with regard to the behavior of the frequently different expansion coefficients between the semiconducting material of the die and the molding compound utilized in the packaging process.
Due to these different expansion coefficients, rim regions of a chip are frequently subject to particular load during the temperature cycling, which is also referred to as TC stress. It is especially in these regions subject to TC stress that various failure scenarios may occur which may present an increased reliability risk for the actual devices.
Such risks are to be avoided, if possible, especially in the chip rim area. For a very large number of devices, it is in the very rim area of the chip that metallic structures are arranged which are implemented, for example, for contacting functional structures of the device. With (vertical) transistors, problems occur, for example, with regard to the reliability in the area of the so-called gate runner structure, which often extends in the area of the chip rim and serves for contacting the gate electrodes of the vertical transistors. In the case of the example of a gate runner structure, it may occur that in the worst case the gate runner metal line completely detaches from and is lifted off the chip surface. This effect is also referred to as “lifted metal lines).
In addition, what may also happen is that the metal structure concerned, for example, the gate runner metal line, still remains adhered to the chip surface, but due to the TC load was shifted back and forth so much that, at the end of a respective TC test, it is noticeably shifted away from its original position in several places. This effect is also referred to as “shifted metal line”.
Such shifted metal structures, or shifted metal lines, are frequently also clearly different in the cross-sectional shape. For example, at the beginning of the test they have an approximately symmetrical trapezoid shape, whereas a highly sheared trapezoid may often be observed at the end of such a test.
Such reliability risks as may quite possibly occur, for example, merely due to the heat generated in the device concerned, depending on the application of the future device, may thus lead to a total failure of the device, since individual functional areas of the device are no longer or no longer fully connected. If, for example in the case of a (vertical) transistor, the gate runner structure becomes detached or shifted, some cells in the area of the cell field of the device concerned which includes the actual transistor structures can no longer be controlled, so that the electric characteristics of the vertical transistor will change over the course of the operation.
Thus, if parts of the actual cell field of the vertical transistor fail because of metal structures that have been lifted off or have been shifted, it may occur, during further operation, that the remaining cells of the cell field become overloaded, so that eventually the vertical transistor, or the device concerned, may be destroyed during operation.